Workshops

In this page you will find information about past or future workshop co-organized by the E2SWITCH project.
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Final Workshop
Energy Efficient Tunnel FET Switches and Circuits
10 November 2017
IMEC, Belgium

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This one-day workshop was organized for the closure of the E2SWITCH EU programme on Energy Efficient Tunnel FET Switches and Circuits and highlighted the results obtained within the program and complemented by external speakers.
Steep transistors with subthreshold swings less than 60 mV/decade are attracting attention worldwide to continue the scaling roadmap and enable electronic systems operating at 300 mV and below. Transistors based on inter-band tunneling (TFETs) are promising and have seen important development in the last years, but there is still no consensus on materials or device architecture, on the mechanisms limiting current performance, on the exact field and conditions of application. In this workshop, the achievements of E2SWITCH project were presented and discussed: fabrication of lateral and vertical IIIV and IV TFETs, TCAD simulations, analytical modelling, and digital and analog circuits benchmarks. These focused presentations were combined with presentations by invited speakers opening the discussion to future prospects and challenges.

The workshop was paired with the Beyond CMOS week, an annual one week course organized by imec Academy.
Organisers
E2SWITCH Project
imec, Belgium
Contact
Marie Garcia Bardon
Marie.GarciaBardon@imec.be
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Steep Transistors Workshop 2016
Energy Efficient Computing Devices and Circuits
11–12 September 2016
EPFL, Lausanne
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Following the first successful workshop at University of Notre Dame, USA, a second workshop related to Steep Slope Transistors has been arranged in combination with the ESSDERC conference at EPFL, Lausanne, Switzerland. Steep transistors with subthreshold swings less than 60 mV/decade are attracting attention worldwide due to their promise to enable electronic systems operating at 300 mV and below. Interband tunneling or internal gain mechanisms in the gate enable the steep onset of current with gate voltage. This field has seen dramatic development over the last few years, however there is yet no consensus on materials or device architecture, and the mechanisms limiting current performance are the subject of wide study. There are an increasing number of projections about the application space for these transistors, which is now extending beyond digital into the analog domain. This two-day workshop at the EPFL was build on the experiences from the first workshop to refine understanding and accelerate the development by discussions on electrostatics, influence on defects, materials selection, as well as digital and analogue metrics.
The workshop format followed the organization at the first workshop with short focused presentations given by invited speakers that were combined with focused discussion sessions guided by invited chairs and panelists. The workshop included in the ESSDERC framework and may thus be selected by all participants for a special fee, depending on the participation in the ESSDERC conference. Besides the workshop, a focus session on “Implementation of Steep Slope Transistors for Circuit Applications” has been arranged at the ESSDERC conference.
Organisers
Lars-Erik Wernersson
Lund University, Sweden
E2SWITCH Project
Alan Seabaugh
University of Notre Dame, Indiana
SRC/STARnet Center for Low Energy Systems Technology (LEAST)
Kirsten Moselund
IBM Zuerich, Switzerland
E2SWITCH Project
Aaron Thean
IMEC, Belgium
E2SWITCH Project
Eli Yablonovitch
University of California Berkeley, USA
SRC/STARnet Center for Low Energy Systems Technology (LEAST)
Adrian Ionescu
EPFL, Switzerland
E2SWITCH Project
The organizers are from the European E2SWITCH consortium, the SRC/STARnet Center for Low Energy Systems Technology (LEAST), and the Center for Energy Efficient Electronics Science (E3S). These centers are actively developing steep transistors.
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Steep Transistors Workshop 2015
Energy Efficient Computing Devices and Circuits
5–6 October 2015
University of Notre Dame
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Steep transistors with subthreshold swings less than 60 mV/decade are attracting attention worldwide due to their promise to enable electronic systems operating at 300 mV and below. Interband tunneling or internal gain mechanisms in the gate enable the steep onset of current with gate voltage. This field has seen dramatic development over the last few years, however there is yet no consensus on materials or device architecture, and the mechanisms limiting current performance are the subject of wide study. There are an increasing number of projections about the application space for these transistors, which is now extending beyond digital into the analog domain. To refine understanding and accelerate development of these transistors, there has been a two- day workshop at the University of Notre Dame sponsored by the Semiconductor Research Corporation (SRC) and DARPA through the Semiconductor Technology Advanced Research Network (STARnet). This was an invited meeting of the leading researchers in steep transistor development, including participants from Europe, Asia, and the U.S. The intent of the two-day meeting was to share progress, improve understanding, and assess directions.
Presentations
Organisers
Alan Seabaugh
University of Notre Dame, Indiana
SRC/STARnet Center for Low Energy Systems Technology (LEAST)
Lars-Erik Wernersson
Lund University, Sweden
E2SWITCH Project
In the Quest of Zero Power
Energy Efficient Computing Devices and Circuits
26 September 2014
Venice

The 1st workshop of the E2SWITCH project entitled "In the Quest of Zero Power: Energy Efficient Computing Devices and Circuits" was held on September 26th, 2014 in Venice as satellite event to the international conference ESSDERC/ESSCIRC 2014. It was conducted as a scientific dissemination, networking and exploitation event of the E2SWITCH project at the end of the 1st year of work.

The workshop included a series of presentations dealing with state of the art advancements in Tunnel FETs as most promising energy efficient device candidates able to reduce the voltage supply of integrated circuits (ICs) below 0.25V and be hybridized with CMOS technology. It also served as a platform for the discussion of suitable exploitation tracks for the technique.

The programme featured focused reports on DC/AC benchmarking for complementary n- and p-type Tunnel FETs, compact models for digital and analog/RF, device scalability, operational reliability and ITRS metrics. The international keynote invited speakers from USA (prof. Alan Seabaugh) and France (Dr. Francis Balestra and Dr. Costin Anghel) provided vision and opinions from outside the E2-SWITCH Consortium.

The workshop was open to the whole ESSDERC/ESSCIRC audience and to other speakers who attended only the workshop day; the profile of the 25 registrants was very diverse, ranging from PhD students and researchers to industry representatives from both the consortium and the public.

Overall, the different presentations and interactions pointed out the importance and the significant advancement made by the Tunnel FET technology in the last year and its importance as one of the very few device candidates that can offer added value to the well established advanced silicon CMOS.

Workshop programme

SpeakerTitle (click to download the presentation)
Adrian M. Ionescu, EPF Lausanne, SwitzerlandIntroduction: the E2SWITCH project
Alan Seabaugh, University of Notre Dame, USAKeynote 1: Tunnel FETs: the promise and the reality
Qing-Tai Zhao, Siegfried Mantl, Forschungszentrum Jülich, GermanyStrained Si nanowireTFETs and circuits
Pierpaolo Palestri, Luca Selmi, University of Udine, ItalySimulation of Tunnel FETs for accurate performance prediction at device and circuit level
Francis Balestra, INP-CNRS, Grenoble, FranceKeynote 2: European structuring, roadmapping and networking
Kirsten Moselund, M.Borg, H. Schmid, D. Cutaia, Heike Riel, IBM Zurich, SwitzerlandlnAs/Si heterostructure tunnel FETs
Morin Dehan, IMEC, BelgiumLow power Tunnel FET circuits: challenges and opportunities
Costin Anghel, Andrei Vladimirescu, Amara Amara, ISEP, FranceKeynote 3: Benefits of SRAM design with tunnel FETs
Lars-Erick Wernersson, University of Lund, SwedenTunnel FETs for digital and analog/RF applications
Adrian M. Ionescu, Nilay Dagtekin, Arnab Biswas, EPF Lausanne, SwitzerlandComputing and sensing with subthermal swing devices