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Steep transistors with subthreshold swings less than 60 mV/decade are attracting attention worldwide to continue the scaling roadmap and enable electronic systems operating at 300 mV and below. Transistors based on inter-band tunneling (TFETs) are promising and have seen important development in the last years, but there is still no consensus on materials or device architecture, on the mechanisms limiting current performance, on the exact field and conditions of application. In this workshop, the achievements of E2SWITCH project were presented and discussed: fabrication of lateral and vertical IIIV and IV TFETs, TCAD simulations, analytical modelling, and digital and analog circuits benchmarks. These focused presentations were combined with presentations by invited speakers opening the discussion to future prospects and challenges.
The workshop was paired with the Beyond CMOS week, an annual one week course organized by imec Academy.


The workshop format followed the organization at the first workshop with short focused presentations given by invited speakers that were combined with focused discussion sessions guided by invited chairs and panelists. The workshop included in the ESSDERC framework and may thus be selected by all participants for a special fee, depending on the participation in the ESSDERC conference. Besides the workshop, a focus session on “Implementation of Steep Slope Transistors for Circuit Applications” has been arranged at the ESSDERC conference.


The 1st workshop of the E2SWITCH project entitled "In the Quest of Zero Power: Energy Efficient Computing Devices and Circuits" was held on September 26th, 2014 in Venice as satellite event to the international conference ESSDERC/ESSCIRC 2014. It was conducted as a scientific dissemination, networking and exploitation event of the E2SWITCH project at the end of the 1st year of work.
The workshop included a series of presentations dealing with state of the art advancements in Tunnel FETs as most promising energy efficient device candidates able to reduce the voltage supply of integrated circuits (ICs) below 0.25V and be hybridized with CMOS technology. It also served as a platform for the discussion of suitable exploitation tracks for the technique.
The programme featured focused reports on DC/AC benchmarking for complementary n- and p-type Tunnel FETs, compact models for digital and analog/RF, device scalability, operational reliability and ITRS metrics. The international keynote invited speakers from USA (prof. Alan Seabaugh) and France (Dr. Francis Balestra and Dr. Costin Anghel) provided vision and opinions from outside the E2-SWITCH Consortium.
The workshop was open to the whole ESSDERC/ESSCIRC audience and to other speakers who attended only the workshop day; the profile of the 25 registrants was very diverse, ranging from PhD students and researchers to industry representatives from both the consortium and the public.
Overall, the different presentations and interactions pointed out the importance and the significant advancement made by the Tunnel FET technology in the last year and its importance as one of the very few device candidates that can offer added value to the well established advanced silicon CMOS.
Workshop programme
Speaker | Title (click to download the presentation) |
---|---|
Adrian M. Ionescu, EPF Lausanne, Switzerland | Introduction: the E2SWITCH project |
Alan Seabaugh, University of Notre Dame, USA | Keynote 1: Tunnel FETs: the promise and the reality |
Qing-Tai Zhao, Siegfried Mantl, Forschungszentrum Jülich, Germany | Strained Si nanowireTFETs and circuits |
Pierpaolo Palestri, Luca Selmi, University of Udine, Italy | Simulation of Tunnel FETs for accurate performance prediction at device and circuit level |
Francis Balestra, INP-CNRS, Grenoble, France | Keynote 2: European structuring, roadmapping and networking |
Kirsten Moselund, M.Borg, H. Schmid, D. Cutaia, Heike Riel, IBM Zurich, Switzerland | lnAs/Si heterostructure tunnel FETs |
Morin Dehan, IMEC, Belgium | Low power Tunnel FET circuits: challenges and opportunities |
Costin Anghel, Andrei Vladimirescu, Amara Amara, ISEP, France | Keynote 3: Benefits of SRAM design with tunnel FETs |
Lars-Erick Wernersson, University of Lund, Sweden | Tunnel FETs for digital and analog/RF applications |
Adrian M. Ionescu, Nilay Dagtekin, Arnab Biswas, EPF Lausanne, Switzerland | Computing and sensing with subthermal swing devices |