Lund university's TFET work short-listed for Compound Industry Award

The TFET work of E2SWITCH partner Lund University was nominated for the Compound Industry Awards 2017 (innovation award).

MOSFET scaling has for several decades been the main path to increase the performance of Si CMOS technology. As a result, the transistor density in the circuits has steadily increased. Since the subthreshold swing (S) for a thermionic device does not scale below 60 mV/dec., this has resulted in increased power density, which has become the main limitation.

To achieve voltage scaling without off-current increase, there is a need for devices with a subthreshold swing lower than 60mV/dec. These are so called steep slope devices, of which the Tunneling Field-Effect Transistor (TFET) is the most promising candidate [1-2]. The TFET operation rely on tunneling-based energy filtering that prevents electrons with high thermal energy to enter the channel thereby enabling sub-60 mV/dec. subthreshold swing. So far, few reports exist of TFETs with S below 60 mV/dec. usually with current levels far below any useful operation range [3-8].

Lund university presents a vertical nanowire InAs/GaAsSb/GaSb heterojunction TFET integrated on a Si substrate with Smin = 48 mV/dec. with I60 = 0.31 μA/μm at VDS = 0.3 V and IDS = 10.6 μA/μm for Ioff = 1nA/um at VDS = 0.3 V. The device achieves an intrinsic gain of 2400 and a transconductance efficiency of 50 V-1. Our novel heterostructure design enabled by the reduced constraint for lattice matching in the bottom up nanowire growth in combination with aggressively scaled dimensions and a gateall-around geometry demonstrate that III-V TFETs are viable alternative both for low-power logic and analog applications.

[1] A.C. Seabaugh, Q. Zhang, Proc. IEEE, Vol. 98, No. 12, pp. 2095–2110, 2010
[2] A. M. Ionescu, H. Riel, Nature, Vol. 479, No. 7373, pp. 329–337, 2011
[3] Q. Huang et. al., in Electron Devices Meeting (IEDM), 2012 IEEE International, pp. 8.5.1 – 8.5.4
[4] L. Knoll et. al., Electron Device Letters, IEEE, Vol. 34, no. 6, pp. 813 – 815, 2013
[5] S. H. Kim et. al., in Proc. VLSI Symp.Tech. Dig., 2012, pp. 178-179
[6] K. Tomioka et. al., in Proc. VLSI Symp.Tech. Dig., 2012, pp. 47-48
[7] T. Krishnamohan et. al., in Electron Devices Meeting (IEDM), 2008 IEEE International, pp. 947 – 949
[8] G. Dewey et. al., in Electron Devices Meeting (IEDM), 2011 IEEE International, pp. 33.6.1–33.6.4